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SDRAM and NVRAM may share the LPDDR2 bus
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6-9-2008 4:00 AM
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microblues
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구체적인 정보 필요
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<div style="margin: 12px 0px; font-family: arial; color: #333333; background: #ffffff; border: solid 4px #e5e5e5; width: 100%; clear: left;"><div class="CM_CTB_Content_Wrap" style="margin: 0px; padding: 0px;background-color: #ffffff;"><div style="border-bottom: solid 1px #dcdcdc; white-space: nowrap; margin-bottom: 8px; background-color: #eeeeee ;background-image: url(http://clipmarks.com/images/source-bg.gif); background-repeat: repeat-x; height: 24px; line-height: 24px; vertical-align: middle; padding-bottom: 4px; color: #666666; font-size: 10px;" ><a href="http://clipmarks.com/clip-to-blog/" title="see clips that are hot right now"><img src="http://content.clipmarks.com/blog_embed/9d70e393-5117-41e3-9cb3-6248e3985ac3/05E298E8-7A8A-4268-B7D1-9C6278271618/" alt="" width="19" height="19" border="0" style="vertical-align: middle; margin: 0px 4px; display: inline; border: none; float:none;" /></a>clipped from <a title="http://www.eetimes.com/rss/showArticle.jhtml?articleID=208402252&cid=RSSfeed_eetimes_newsRSS" href="http://www.eetimes.com/rss/showArticle.jhtml?articleID=208402252&cid=RSSfeed_eetimes_newsRSS" style="font-size: 11px;">www.eetimes.com</a></div><blockquote style="text-align: left; padding: 0px 8px; margin: 4px 0px 8px 0px; background: transparent; border: none;" cite="http://www.eetimes.com/rss/showArticle.jhtml?articleID=208402252&cid=RSSfeed_eetimes_newsRSS"><SPAN class="storyheadline">Lower voltage next goal for low-power DDR</SPAN></blockquote><div style="height: 2px; font-size: 2px; background: #dcdcdc; border-bottom: solid 1px #f5f5f5; margin: 2px 4px;"></div><blockquote style="text-align: left; padding: 0px 8px; margin: 4px 0px 8px 0px; background: transparent; border: none;" cite="http://www.eetimes.com/rss/showArticle.jhtml?articleID=208402252&cid=RSSfeed_eetimes_newsRSS"><P> Low-power <A href="http://www.eetimes.com/encyclopedia/defineterm.jhtml?term=DDR2&x=&y=">DDR2</A> (LPDDR2), a next-generation low-power memory technology for mobile and embedded designs that's being defined by companies participating in Jedec standards, offers higher speed, lower- voltage operation, larger capacities and lower pin count than the current generation--and lets nonvolatile memory share the same <A href="http://www.eetimes.com/encyclopedia/defineterm.jhtml?term=bus&x=&y=">bus</A> as SDRAM. </P></blockquote><div style="height: 2px; font-size: 2px; background: #dcdcdc; border-bottom: solid 1px #f5f5f5; margin: 2px 4px;"></div><blockquote style="text-align: left; padding: 0px 8px; margin: 4px 0px 8px 0px; background: transparent; border: none;" cite="http://www.eetimes.com/rss/showArticle.jhtml?articleID=208402252&cid=RSSfeed_eetimes_newsRSS"><P> PC memory has been designed so that many memories can share the same address bus; there can be up to 18 memories on a single unbuffered DIMM, necessitating a single-data-rate address bus even with double-data-rate data pins. Since LPDDR memories aren't intended for this kind of high-fanout application, the LPDDR2 spec may take the opportunity to reduce pin count, which can reduce the package size for both the memory and the host processor, and reduce system cost. </P></blockquote></div><div style="margin: 0px 6px 6px 4px;"><table style="font-size: 11px;border-spacing: 0px;padding: 0px;" cellpadding="0" cellspacing="0" width="100%"><tr><td style="background:transparent;border-width:0px;padding:0px;"> </td><td align="right" style="background:transparent;border-width:0px;padding:0px;width:107px" width="107"><a href="http://clipmarks.com/share/05E298E8-7A8A-4268-B7D1-9C6278271618/blog/" title="blog or email this clip"><img src="http://content8.clipmarks.com/images/c2b-foot.png" border="0" alt="blog it" width="107" height="17" style="border-width:0px;padding:0px;margin:0px;" /></a></td></tr></table></div></div>
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